In a recent article published in Nature, researchers developed a 300-mm cryogenic probing process to obtain high-volume data on spin qubit devices across full wafers. They optimized an industry-compatible process to fabricate spin qubit devices on a low-disorder host material, enabling automated probing of single electrons in spin qubit arrays across 300-mm wafers.
a. Charge-stability diagram showing the configuration in which electron temperature is extracted. b. 1D measurement across the transition indicated by the dashed red line in a with theoretical fit overlaid. Image Credit: https://www.nature.com/articles/s41586-024-07275-6
Background
Building a fault-tolerant quantum computer requires a substantial number of physical qubits. Recently, silicon quantum dot spin qubits—qubits based on silicon electrons—have achieved two-qubit and single-qubit fidelities above 99 %, meeting the thresholds for error correction.
Currently, integrated spin qubit arrays have reached sizes of up to six quantum dots, with larger platforms in both two-dimensional (2D) and one-dimensional (1D) configurations also demonstrated. However, to realize real-world applications, the number of physical qubits must significantly increase. Therefore, spin qubit devices need to be fabricated with uniformity, volume, and density comparable to classical computing chips, which now contain billions of transistors.
Challenges in Scaling Spin Qubits
Fabricating spin qubit devices using a similar infrastructure as classical computing chips can facilitate the development of fault-tolerant quantum computers using the spin qubit technology and unlock the spin qubits' potential for scaling.
This is because spin qubit technology possesses inherent advantages for scaling due to the approximate qubit size of 100 nm and built-in compatibility with modern complementary metal-oxide-semiconductor (CMOS) manufacturing infrastructure, specifically in the case of silicon-based devices.
Currently, yield and process variation are the major challenges for spin qubits. Additionally, the cryogenic electrical testing bottleneck hinders the scaling of solid-state quantum technologies like superconducting and topological qubits and spin qubits. Thus, the cryogenic device testing scale must maintain pace with the increasing fabrication complexity to ensure efficient device screening and improve statistical metrics like voltage variation and qubit yield. Yield and process variation in quantum devices can be improved by combining process changes with statistical measurements of indicators like component yield and voltage variation.
The Study
In this study, researchers proposed a testing process using a cryogenic 300-mm wafer prober to obtain high-volume data on the performance of hundreds of industry-manufactured spin qubit devices at 1.6 K across full wafers. They combined low process variation with a low-disorder host material to optimize an industry-compatible process for spin qubit device fabrication on silicon/silicon-germanium (Si/SiGe) heterostructures.
These advancements were synergistic: the development of the full-wafer cryogenic test capability enabled complex 300-mm fabrication process optimization, while the optimized fabrication process improved the reliability of the devices, allowing high-fidelity automated measurements across wafers.
Collectively, these advancements culminated in automated single-electron probing in spin qubit arrays across 300-mm wafers. The spin qubit devices were synthesized in Intel's D1 factory, where CMOS logic processes are developed. A Si/SiGe heterostructure grown on 300-mm silicon wafers was used as the host material.
Researchers selected this structure to exploit the prolonged electron spin coherence in silicon and its applicability for multiple qubit encodings. All patterning was performed using optical lithography, with extreme ultraviolet lithography employed for quantum dot gate patterning in a single pass.
Additionally, all device sub-components were fabricated using fundamental industry techniques such as chemical-mechanical polishing, etching, and deposition. The cryo-prober used in this work, manufactured by AEM Afore and Bluefors, can load and cool 300-mm wafers to a base temperature of 1.0 K at the chuck and an electron temperature of 1.6 ± 0.2 K. Thousands of test structures and spin qubit arrays on the wafer were measured after cooldown.
Significance of the Study
Low process variation and high yield were successfully achieved across the 300-mm wafer using the proposed approach. The proposed cryogenic testing method provided fast feedback to enable the CMOS-compatible fabrication process's optimization, resulting in low process variation and high yield.
Using this proposed system, measurements of the spin qubits' operating point were successfully automated, and the transitions of single electrons were thoroughly investigated across full wafers. Results obtained by analyzing the random variation in single-electron operating voltages demonstrated that the optimized fabrication process results in low levels of disorder at the 300-mm scale.
The high device yield combined with the cryogenic wafer prober enabled a simple path from device fabrication to the investigation of spin qubits, which eliminated failures due to electrostatics or yield at the dilution refrigerator stage. Overall, an extensible and large unit cell of up to 12 qubits was realized using a high-volume cryogenic testing method, an all CMOS-industry-compatible fabrication process with low process variation, and a low-disorder host material/Si/SiGe.
To summarize, the findings of this study established a new standard for the reliability and scale of spin qubit devices and paved the way for more complex and much larger spin qubit arrays of the future.
Journal Reference
Neyens, S., et al. et al. (2024). Probing single electrons across 300-mm spin qubit wafers. Nature, 629(8010), 80-85. https://doi.org/10.1038/s41586-024-07275-6, https://www.nature.com/articles/s41586-024-07275-6
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